Patent · US Active

Semiconductor circuit device and a system for testing a semiconductor apparatus

US7331005B2 · kind B2 · utility

2Cited by

7References

23Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ralf Arnold · Aalen, DE
Gerd Frankowsky · Wappingers Falls, US
Wolfgang Anton Spirkl · Germering, DE

Key dates

Filing date	Jul 26, 2005
Grant date	Feb 12, 2008
Priority date	—
Expiry date	Jul 17, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3016
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.