Dielectric passivation for semiconductor devices
US7332795B2 · kind B2 · utility
83Cited by
12References
49Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier layer covering at least a portion of the one surface adjacent the control contact, the dielectric barrier layer having a bandgap greater than the bandgap of the Group III nitride and a conduction band offset from the conduction band of the Group III nitride; and a dielectric protective layer covering the remainder of the Group III nitride surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.