Optimizing critical dimension uniformity utilizing a resist bake plate simulator
US7334202B1 · kind B1 · utility
10Cited by
3References
25Claims
0Family size
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Key dates
| Filing date | Jun 3, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jun 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.