Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US7335536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Nov 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.