Device with stepped source/drain region profile

US7335959B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Giuseppe Curello · Portland, US
• Bernhard Sell · Dresden, DE
• Sunit Tyagi · Portland, US
• Chris Auth · Portland, US

Key dates

• Filing date: Jan 6, 2005
• Grant date: Feb 26, 2008
• Expiry date: Dec 9, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.