Layout for equalizer and data line sense amplifier employed in a high speed memory device
US7336518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | May 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.