Electronic device and method for operating a memory circuit
US7336533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Mar 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage. This bi-directional low voltage drop low loss switch can increase the write margin of the memory cell wherein the high impedance read port can provide increased isolation for the stored value during the read phase increasing the performance of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.