Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage
US7338908B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2003 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Feb 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.