Metallization performance in electronic devices
US7339274B2 · kind B2 · utility
4Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Nov 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.