Technique for combining scan test and memory built-in self test
US7340658B2 · kind B2 · utility
19Cited by
5References
35Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Sep 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.