Markus Seuring
7Patents
4h-index
6Co-inventors
42Inventor score
Filing activity: Dec 10, 2004 → Aug 12, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7340658B2 | Technique for combining scan test and memory built-in self test | Physics | 19 | Expired |
| US7689884B2 | Multicore chip test | Physics | 13 | Active |
| US7653845B2 | Test algorithm selection in memory built-in self test controller | Physics | 10 | Active |
| US7673208B2 | Storing multicore chip test data | Physics | 6 | Active |
| US9885752B2 | Test apparatus for generating reference scan chain test data and test system | Physics | 1 | Active |
| US9164726B2 | Apparatus for determining a number of successive equal bits preceding an edge within a bit stream and apparatus for reconstructing a repetitive bit sequence | Physics | 1 | Active |
| US8307249B2 | At-speed bitmapping in a memory built-in self-test by locking an N-TH failure | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.