Method and system for reduction of XOR/XNOR subexpressions in structural design representations
US7340694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.