Capacitorless 1-transistor DRAM cell and fabrication method
US7341904B2 · kind B2 · utility
92Cited by
9References
19Claims
0Family size
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Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jul 9, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
Abstract
A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.