Field effect transistors with dielectric source drain halo regions and reduced miller capacitance
US7342266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.