CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
US7342268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.