Method to increase mechanical fracture robustness of porous low k dielectric materials
US7342315B2 · kind B2 · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2005 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Apr 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.