Testing memory units in a digital circuit
US7343532B2 · kind B2 · utility
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5References
6Claims
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Key dates
| Filing date | May 20, 2003 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a memory unit in a digital circuit includes storing a test pattern on a register of the digital circuit. The register is then selected by providing an activation signal to a selection unit. The memory unit is then tested with the test pattern stored in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.