Open digit line array architecture for a memory array
US7345937B2 · kind B2 · utility
22Cited by
11References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 7, 2006 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Aug 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.