Apparatus and methods for providing in-chip microtargets for metrology or inspection
US7346878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are techniques and apparatus for providing metrology or inspection targets in-chip. That is, targets are integrated within the product device or die area. In general terms, the present invention provides techniques for enabling inspection or metrology on targets within the die or active area. Said in another way, target structures are inserted within the die or active area. In one embodiment, a set of rules are provided for integrating test structures within the die. For example, these rules may be implemented by one or more design engineers or by place-and-route tools which automatically generate the die layout pattern and thereafter insert the target structures into the die layout pattern based on these rules. Location data of each target is then retained during the layout generation and provided to one or more inspection or metrology tools and/or metrology engineers so that each target may be found and then inspected or measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.