Formation of memory cells and select gates of NAND memory arrays
US7348236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jul 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the second conductive layer self align with and are disposed on sidewalls of the first conductive layer. The first conductive layer is disposed on a first dielectric layer that is disposed on a substrate. A second dielectric layer is formed overlying the first conductive layer and the remaining portions of the second conductive layer. A third conductive layer is formed on the second dielectric layer. A fourth conductive layer is formed on the third conductive layer. For the select gate, the fourth conductive layer also passes through the third conductive layer and the second dielectric layer to electrically connect the conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.