Wafer scale thin film package
US7348261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2003 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.