Test structures and models for estimating the yield impact of dishing and/or voids
US7348594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.