Flash memory cell having reduced floating gate to floating gate coupling
US7348618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.