Ferroelectric memory arrangement
US7348619B2 · kind B2 · utility
2Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Dec 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.