Reducing read disturb for non-volatile storage
US7349258B2 · kind B2 · utility
31Cited by
38References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.