Arithmetic circuit with balanced logic levels for low-power operation
US7349938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by the signals within the adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.