Method and apparatus for issuing instructions from an issue queue in an information handling system
US7350056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.