Non-volatile memory cells and methods for fabricating non-volatile memory cells

US7352018B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Specht · Munich, DE
• Franz Hofmann · Munich, DE
• Johannes Luyken · Birkenfeld, DE

Key dates

• Filing date: Jul 22, 2005
• Grant date: Apr 1, 2008
• Expiry date: Jul 22, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.