Voltage-level converter
US7352209B2 · kind B2 · utility
6Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Apr 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.