Patent · US Active

Variable clocked scan test improvements

US7353470B2 · kind B2 · utility

20Cited by
4References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 18, 2005
Grant dateApr 1, 2008
Priority date—
Expiry dateJun 16, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318552
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.