Method and apparatus for avoiding dicing chip-outs in integrated circuit die

US7354790B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Parthasarathy Rajagopalan · Milpitas, US
• Zafer Kutlu · Menlo Park, US
• Emery Sugasawara · Pleasanton, US
• Charles E. VONDERACH · Livermore, US
• Dilip Vijay · Redwood City, US
• Yogendra Ranade · Fremont, US
• Jeff Hall · Normal, US
• Dwight Manning · San Jose, US

Key dates

• Filing date: May 18, 2005
• Grant date: Apr 8, 2008
• Expiry date: Mar 3, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.