Method of fabricating a stacked integrated circuit package system
US7354800B2 · kind B2 · utility
64Cited by
12References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jun 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.