Gate structure and a transistor having asymmetric spacer elements and methods of forming the same

US7354839B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Andy Wei · Queensbury, US
• Gert Burbach · Dresden, DE
• David C. Greenlaw · Dresden, DE

Key dates

• Filing date: Oct 11, 2005
• Grant date: Apr 8, 2008
• Expiry date: Dec 30, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.