Inventor · Queensbury, NY, US

Andy Wei

213Patents

19h-index

182Co-inventors

89Inventor score

Filing activity: Feb 28, 2002 → Dec 29, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8609510B1	Replacement metal gate diffusion break formation	Electricity	93	Active
US8846491B1	Forming a diffusion break during a RMG process	Electricity	84	Active
US7138320B2	Advanced technique for forming a transistor having raised drain and source regions	Electricity	69	Expired
US8753940B1	Methods of forming isolation structures and fins on a FinFET semiconductor device	Electricity	47	Active
US8603893B1	Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates	Electricity	39	Active
US9362165B1	2D self-aligned via first process flow	Electricity	35	Active
US8114746B2	Method for forming double gate and tri-gate transistors on a bulk substrate	Electricity	35	Active
US8298885B2	Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure	Electricity	34	Active
US9368395B1	Self-aligned via and air gap	Electricity	32	Active
US9431512B2	Methods of forming nanowire devices with spacers and the resulting devices	Electricity	27	Active
US8053273B2	Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process	Electricity	27	Active
US7354839B2	Gate structure and a transistor having asymmetric spacer elements and methods of forming the same	Electricity	26	Expired
US8557666B2	Methods for fabricating integrated circuits	Electricity	25	Active
US8722498B2	Self-aligned fin transistor formed on a bulk substrate by late fin etch	Electricity	23	Active
US7399663B2	Embedded strain layer in thin SOI transistors and a method of forming the same	Electricity	23	Active
US9406775B1	Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints	Electricity	21	Active
US9159630B1	Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme	Electricity	21	Active
US8071442B2	Transistor with embedded Si/Ge material having reduced offset to the channel region	Electricity	19	Active
US6737332B1	Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same	Electricity	19	Expired
US8021942B2	Method of forming CMOS device having gate insulation layers of different type and thickness	Emerging Cross-Sectional Technologies	18	Active
US7354838B2	Technique for forming a contact insulation layer with enhanced stress transfer efficiency	Electricity	17	Active
US7723174B2	CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor	Electricity	16	Active
US9825031B1	Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices	Electricity	16	Active
US7579262B2	Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same	Electricity	16	Active
US9704973B2	Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins	Electricity	16	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.