Thin passivation layer on 3D devices
US7354862B2 · kind B2 · utility
7Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Aug 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a with a Langmuir-Blodgett technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.