Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7355281B2 · kind B2 · utility
44Cited by
25References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Mar 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.