Method of forming an interconnect structure
US7358182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Aug 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.