Method for decreasing sheet resistivity variations of an interconnect metal layer
US7358191B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 24, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Aug 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.