Design analysis tool and method for deriving correspondence between storage elements of two memory models
US7360183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2004 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.