Dual stress liner

US7361539B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Xiangdong Chen · Irvine, US
• Haining Yang · Wappingers Falls, US

Key dates

• Filing date: May 16, 2006
• Grant date: Apr 22, 2008
• Expiry date: Sep 30, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.