Method of forming a nanocluster charge storage device
US7361543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Aug 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.