Method of forming a metal gate in a semiconductor device
US7361565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Feb 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.