Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices
US7362615B2 · kind B2 · utility
14Cited by
38References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.