Testing apparatus and testing method
US7363556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jul 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail memory unit includes a write time measuring section for measuring a write time required for writing said test data per each of said pages, an integrating section for integrating said write time across a plurality of said pages set in advance, and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance. The integrating section further integrates said write time per page group having said predetermined number of pages. The judging section further judges whether or not said page group is defect-free based on an integral value of said write time per said page group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.