Circuit for and method of determining the location of a defect in an integrated circuit
US7363560B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jan 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318519
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.