Integrated circuit selective scaling
US7363601B2 · kind B2 · utility
10Cited by
16References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Nov 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.