Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same
US7364966B2 · kind B2 · utility
3Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.