Method for fabricating semiconductor device
US7365000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jul 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.