Strain inducing multi-layer cap
US7365357B2 · kind B2 · utility
5Cited by
0References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 22, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jan 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.