DRAM layout with vertical FETs and method of formation
US7365385B2 · kind B2 · utility
126Cited by
10References
69Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Oct 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
Abstract
DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.